The present invention relates to a solid-state image-pickup device including a plurality of transfer registers provided for an array of sensors and a method of driving the device.
FIG. 9 is a diagram showing a top view of a related art 1-line linear sensor in a simple and plain manner.
As shown in the figure, the related art linear sensor 50 comprises a sensor array 52, first and second CCD horizontal transfer registers 53 and 54, and a horizontal-horizontal transfer register 55. The sensor array 52 is a plurality of light receiving units 51, or a one-dimensional array of so-called sensor units 51 or opto-electrical conversion units 51. The light receiving units 51 each serve as a pixel.
Transfers of data in the horizontal CCD transfer registers 53 and 54 are 2-phase driven. To be more specific, horizontal drive pulse signals φ1 and φ2 are applied thereto.
In addition, a transfer pulse signal φHH is applied to the horizontal-horizontal transfer register 55.
A signal charge of an even pixel of a sensor unit 51 and a signal charge of an odd pixel of a sensor unit 51 are read out by read-out gates 56e and 56o, respectively which are controlled separately.
To be more specific, a read-out pulse signal φre is applied to the read-out gate 56e for an even pixel while a read-out pulse signal φro is applied to the read-out gate 56o for an odd pixel.
Typical transfer timings in this configuration are shown in FIG. 10.
First of all, when the read-out pulse signal φre is raised to a high level with the horizontal driving pulse signal φh1 set at the high level, the read-out gate 56e is opened to let a signal charge of an even pixel be transferred to the first horizontal CCD transfer register 53.
Next, when the horizontal driving pulse signal φh1 is set at a low level with the transfer pulse signal φHH raised at the high level, the signal charge of the even pixel is transferred from the first horizontal CCD transfer register 53 to the horizontal-horizontal transfer register 55.
Then, when the read-out pulse signal φro and the horizontal driving pulse signal φh2 are raised to the high level at the same time, the read-out gate 56o is opened to let a signal charge of an odd pixel be transferred to the first horizontal CCD transfer register 53.
At that time, since the transfer pulse signal φHH is further set at the low level while the horizontal driving pulse signal φh2 is raised to the high level simultaneously, the signal charge of the even pixel existing in the horizontal-horizontal transfer register 55 is transferred to a transfer unit of the second horizontal CCD transfer register 54, to which pulse signal φh2 is delivered.
Thereafter, normal transfers or horizontal CCD transfers are carried out by the first and second horizontal CCD transfer registers 53 and 54 by raising the 2-phase pulse signal, namely, the horizontal driving pulse signals φh1 and φh2, to a high level alternately to output the signal charges as a signal.
As described above, pixel signals stored in the sensor units 51 of the sensor array 52 are transferred by distributing the signals to a plurality of transfer units in the first and second horizontal CCD transfer registers 53 and 54. As a consequence, in order for the sensor array 52 to allocate the pixel signals to the transfer units, as many read-out gates 56e and 56o and as many read-out pulse signals φre and φro as transfer units of the first and second horizontal CCD transfer registers 53 and 54 are normally required.
In such the configuration of the linear sensor 50, however, timings of the read-out pulse signals φre and φro for reading out signal charges of even and odd pixels respectively are different. As a result, the time difference ΔT between the reading-out timings results in a difference ΔT in accumulation period between the signal charges.
In turn, the difference ΔT in accumulation period causes, among others, sensitivity varying from pixel to pixel and a deviation in signal-charge fetching between pixels.
In addition, since the read-out gates 56e and 56o are provided separately for the even and odd pixels respectively, the configuration of the read-out gates 56e and 56o and the driving pulse signals of the read-out gates 56e and 56o become complex.